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draftv1-0 fujitsu semiconduc t or d a t a s h e e t 32-bit microcontroller cmos fr60lite mb91230 series mb91233l/mb91f233/mb91f233l/mb91v230 n n n n description the mb91230 se r ies is a line of standard microcontroller s , based on a 32-bit high-per f o r mance risc cpu and containing v a r iety of i/o resource s , f or embedded control applications which require high cpu per f o r mance at high speed processing. a udio motor control sto r age:designed to specifications f or embedded control applications which high cpu per f o r mance p o w er processing. the mb91230 se r ies belongs to the fr60lite f amil y . n n n n fe a tures fr60lite cpu ? 32-bit ris c , load/store architecture with a fi v e-stage pipeline ? maxi m um ope r ating frequency: 33.6 mhz (oscillation frequency = 4.2 mhz, oscillation frequency 8- m ultiplier (pll clo c k m ultiplication method) ) ? 16-bit fi x ed length inst r uctions (basic inst r uctions) ? e x ecution speed of inst r uctions : 1 inst r uction per cycle (continued) n n n n p a ck a ges 401-pin ceramic pga 120-pin plastic lqfp 128-pin plastic flga (pga-401c-a02 ) (ftp-120p-m05 ) (lga-128p-m01)
mb91230 series 2 (continued) ? memory-to-memory transfer, bit handling, and barrel shift instructions, etc : instructions suitable for embedded applications ? function entry/exit instructions, multiple-register load/store instructions : instructions adapted for c-language ? register interlock function : facilitates coding in assembler ? built-in multiplier with instruction-level support - 32-bit multiplication with sign : 5 cycles - 16-bit multiplication with sign : 3 cycles ? interrupt (pc and ps save) : 6 cycles (16 priority levels) ? harvard architecture allowing program access and data access to be executed simultaneously ? instruction compatible with fr family ? capacity of built-in rom and rom type - mask rom : 256 kb - flash rom : 256 kb ? capacity of built-in ram : 16 kb ? general-purpose ports : maximum 98 ports(nch of these channels is open-drain port : 4 ports) ? a/d converter (series-parallel type) - resolution : 10-bit : 8 ch (4 ch 2 unit) - conversion time : 1.69 m s (minimum conversion time) ? d/a converter (r-2r type) - resolution : 8-bit : 2 ch (independence) - conversion speed : 0.6 m s (when load capacitance 20 pf) ? external interrupt input : 16 ch ? bit search module (for realos) - function for searching the msb (upper bit) in each word for the first 0 or 1 inverted point ? uart (full-duplex double buffer) : 4 ch - selectable parity on/off - asynchronous (start-stop synchronized) or clock-synchronous communications selectable - internal timer for dedicated baud rate (u-timer) on each channel - external clock can be used as transfer clock - error detection function for parity, frame and overrun ? ppg : 16-bit 6 ch ? up/down counter : 2 ch (8-bit 2 ch or 16-bit 1 ch) ? reload timer : 16-bit 4 ch ? free-run timer : 16-bit 2 ch ? watch timer : 15-bit 1 ch ? pwc : 8-bit 2 ch ? input capture : 2 ch (interface with free-run timer 0) ? output compare : 4 ch (free-run timer 0 and output compare unit 0/1 interlock each other, free-run timer 1 and output compare units 2/3 interlock with one another) ? lcd controller : seg00 to seg31/com0 to com3 (also serving as a port) ? clock monitor (peripheral clock output function) : 1 ch ? timebase/watchdog timer (26-bit) ? real-time clock (counting even with the real-time clock stopped) ? low power consumption mode ? sleep/stop function ? package : lqfp-120 ? technology : cmos 0.35 m m ? power supply ? dual power supply configuration [internal logic 3.3 v, i/o 5.5 v(3.3 v for adc and dac input/output)] note : do not set the external bus mode in which the mb91230 series cannot operate.
mb91230 series 3 n n n n pin assignment (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p26/sck2 p27/sin3 p30/sot3 p31/sck3 p32/ain0 p33/bin0 p34/zin0 p35/ain1 p36/bin1 p37/zin1 p40/ppg0 p41/ppg1 x0a x1a v cc 3b/v cc v ss v cc 3 p42/ppg2 p43/ppg3 p44/tot0 p45/tot1 p46/tot2 p47/ckot p50/int8 p51/int9 p52/int10 p53/int11/ppg4 p54/int12/ppg5 p55/int13/tin2 p56/int14/tin1 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 init md0 md1 md2 p73/com3 p72/com2 p71/com1 p70/com0 p67/seg31 * p66/seg30 * p65/seg29 * p64/seg28 * pb3/seg27 pb2/seg26 v ss v cc pb1/seg25 pb0/seg24 pa7/seg23 pa6/seg22 pa5/seg21 pa4/seg20 pa3/seg19 pa2/seg18 pa1/seg17 pa0/seg16 p97/seg15 p96/seg14 p95/seg13 p94/seg12 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p57/int15/tin0/adtg0 pf3/tot3 pf4/tin3/adtg1 pd0/da0 pd1/da1 av cc avrh av ss pc0/an0 pc1/an1 pc2/an2 pc3/an3 pc4/an4 pc5/an5 pc6/an6 pc7/an7 v ss v cc 3io p80/seg0 p81/seg1 p82/seg2 p83/seg3 p84/seg4 p85/seg5 p86/seg6 p87/seg7 p90/seg8 p91/seg9 p92/seg10 p93/seg11 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 p25/sot2p p24/sin2p p23/pwi1/op3 p22/pwi0/op2 p21/cki1/op1 p20/cki0/op0 p17/int7 p16/int6 p15/int5 p14/int4 p13/int3 p12/int2 x0 x1 v ss v cc p11/int1 p10/int0 p07/ic1 p06/ic0 p05/sck1 p04/sot1 p03/sin1 p02/sck0 p01/sot0 p00/sin0 v3 v2 v1 v0 (top view) (lqfp-120) * : open-drain
mb91230 series 4 (continued) ~ mb91f233l m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 h1 h2 h3 h4 h9 h10 h11 h12 g1 g2 g3 g4 g9 g10 g11 g12 f1 f2 f3 f4 f9 f10 f11 f12 e1 e2 e3 e4 e9 e10 e11 e12 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 a1 m l k j h g f e d c b a a2a3a4a5a6a7a8a9a10a11a12 123456789101112 top view index
mb91230 series 5 mb91[f]233llga-ge1 pin -pad correspondence table (lga-128p-m01) (continued) lqfp120 no. flga no. (jedec no.) signal name lqfp120 no. flga no. (jedec no.) signal name lqfp120 no. flga no. (jedec no.) signal name 1 a1 p26/sck2 98 c9 p03/sin1 18 g1 p42/ppg2 120 a2 p25/sot2 93 c10 v2 15 g2 v cc 3b 117 a3 p22/pwi0/ op2 85 c11 p72/com2 (*1) g3 v cc 3 114 a4 p17/int7 87 c12 md2 17 g4 v cc 3 ? a5 nc 10 d1 p37/zin1 71 g9 pa6/ seg22 109 a6 p12/int2 6 d2 p33/bin0 75 g10 v cc 107 a7 x1 8 d3 p35/ain1 74 g11 pb1/ seg25 103 a8 p10/int0 119 d4 p24/sin2 77 g12 pb2/ seg26 100 a9 p05/sck1 111 d5 p14/int4 21 h1 p45/tot1 97 a10 p02/sck0 ? d6 nc 19 h2 p43/ppg3 94 a11 v3 101 d7 p06/ic0 23 h3 p47/ckot 91 a12 v0 95 d8 p00/sin0 20 h4 p44/tot0 4 b1 p31/sck3 89 d9 md0 65 h9 pa0/ seg16 118 b2 p23/pwi1/ op3 86 d10 p73/com3 72 h10 pa7/ seg23 115 b3 p20/cki0/ op0 82 d11 p67/ seg31* 69 h11 pa4/ seg20 112 b4 p15/int5 84 d12 p71/com1 73 h12 pb0/ seg24 110 b5 p13/int3 13 e1 x0a 24 j1 p50/int8 106 b6 v ss 9 e2 p36/bin1 22 j2 p46/tot2 104 b7 p11/int1 12 e3 p41/ppg1 26 j3 p52/int10 99 b8 p04/sot1 5 e4 p32/ain0 29 j4 p55/int13/ tin2 96 b9 p01/sot0 81 e9 p66/ seg30* 35 j5 pd1/da1 92 b10 v1 83 e10 p70/com0 40 j6 pc1/an1 88 b11 md1 80 e11 p65/ seg29* 47 j7 v ss 90 b12 init ? e12 nc 50 j8 p81/seg1
mb91230 series 6 (continued) lqfp120 no. flga no. (jedec no.) signal name lqfp120 no. flga no. (jedec no.) signal name lqfp120 no. flga no. (jedec no.) signal name 7 c1 p34/zin0 16 f1 v ss 59 j9 p92/ seg10 2 c2 p27/sin3 ? f2 nc 68 j10 pa3/ seg19 3 c3 p30/sot3 14 f3 x1a 66 j11 pa1/ seg17 116 c4 p21/cki1/ op1 11 f4 p40/ppg0 70 j12 pa5/ seg21 113 c5 p16/int6 78 f9 pb3/ seg27 27 k1 p53/ int11/ ppg4 108 c6 x0 79 f10 p64/ seg28* 25 k2 p51/int9 105 c7 v cc 76 f11 v ss 33 k3 pf4/tin3/ adtg1 102 c8 p07/ic1 ? f12 nc 38 k4 av ss 41 k5 pc2/an2 36 l4 av cc 37 m3 avrh 44 k6 pc5/an5 (*2) l5 avrl 39 m4 pc0/an0 48 k7 v cc 3io 43 l6 pc4/an4 42 m5 pc3/an3 53 k8 p84/seg4 45 l7 pc6/an6 46 m6 pc7/an7 56 k9 p87/seg7 49 l8 p80/seg0 ? m7 nc 63 k10 p96/ seg14 52 l9 p83/seg3 51 m8 p82/seg2 62 k11 p95/ seg13 55 l10 p86/seg6 54 m9 p85/seg5 67 k12 pa2/ seg18 58 l11 p91/seg9 57 m10 p90/seg8 30 l1 p56/ int14/ tin1 64 l12 p97/ seg15 60 m11 p93/ seg11 28 l2 p54/ int12/ ppg5 31 m1 p57/ int15/ tin0/ adtg0 61 m12 p94/ seg12 32 l3 pf3/tot3 34 m2 pd0/da0 nc nc pin on the flga version signals added to the flga version (*1) connected to pin 17(v cc 3) on the lqfp120 version (*2) connected to pin 38(av ss ) on the lqfp120 version * : open-drain
mb91230 series 7 n n n n pin description (continued) pin no. pin name circuit type description lqfp flga 1a1 sck2 d uart2 clock input/output. p26 general purpose input/output port. 2c2 sin3 d uart3 data input. p27 general purpose input/output port. 3c3 sot3 b uart3 data output. p30 general purpose input/output port. 4b1 sck3 b uart3 clock input/output. p31 general purpose input/output port. 5e4 ain0 b up/down counter 0 input p32 general purpose input/output port. 6d2 bin0 b up/down counter 0 input p33 general purpose input/output port. 7c1 zin0 b up/down counter 0 input p34 general purpose input/output port. 8d3 ain1 b up/down counter 1 input p35 general purpose input/output port. 9e2 bin1 b up/down counter 1 input p36 general purpose input/output port. 10 d1 zin1 b up/down counter 1 input p37 general purpose input/output port. 11 f4 ppg0 d ppg0 output. p40 general purpose input/output port. 12 e3 ppg1 d ppg1 output p41 general purpose input/output port. 13 e1 x0a ? sub-clock oscillation pin (32 khz) 14 f3 x1a 15 g2 v cc 3b ? power supply pin for backup (internal logic) 16 f1 v ss ? power supply pin (gnd) 17 g4 v cc 3 ? power supply pin (internal logic) 18 g1 ppg2 d ppg2 output. p42 general purpose input/output port. 19 h2 ppg3 d ppg3 output. p43 general purpose input/output port.
mb91230 series 8 (continued) pin no. pin name circuit type description lqfp flga 20 h4 tot0 d reload timer 0 output port. p44 general purpose input/output port. 21 h1 tot1 d reload timer 1 output port. p45 general purpose input/output port. 22 j2 tot2 d reload timer 2 output port. p46 general purpose input/output port. 23 h3 ckot d clock monitor function output pin. p47 general purpose input/output port. 24 j1 int8 c external interrupt input. p50 general purpose input/output port. 25 k2 int9 c external interrupt input. p51 general purpose input/output port. 26 j3 int10 c external interrupt input. p52 general purpose input/output port. 27 k1 ppg4 c ppg4 output. int11 external interrupt input. p53 general purpose input/output port. 28 l2 ppg5 c ppg5 output. int12 external interrupt input. p54 general purpose input/output port. 29 j4 tin2 c reload timer 2 event input pin int13 external interrupt input. p55 general purpose input/output port. 30 l1 tin1 c reload timer 1 event input pin int14 external interrupt input. p56 general purpose input/output port. 31 m1 adtg0 c external trigger input pin of a/d converter 0. tin0 reload timer 0 event input pin int15 external interrupt input. p57 general purpose input/output port. 32 l3 tot3 d reload timer 3 output port. pf3 general purpose input/output port.
mb91230 series 9 (continued) pin no. pin name circuit type description lqfp flga 33 k3 adtg1 d external trigger input pin of a/d converter 1. tin3 reload timer 3 event input pin pf4 general purpose input/output port. 34 m2 da0 f d/a converter 0 output pin. pd0 general purpose input/output port. 35 j5 da1 f d/a converter 1 output pin. pd1 general purpose input/output port. 36 l4 av cc ? analog power supply (for a/d, d/a converter) . 37 m3 avrh ? analog reference power supply (for a/d, d/a converter) . 38 k4 av ss ? gnd level input for analog circuit (for a/d, d/a converter) . 39 to 46 m4, j6, k5, m5, l6, k6, l7, m6 an0 to an7 e analog input pin for a/d converter. pc0 to pc7 general purpose input/output port. 47 j7 v ss ? power supply pin (gnd) 48 k7 v cc 3io ? power supply pin (analog-shared pin i/o) 49 to 56 l8, j8, m8, l9, k8, m9, l10, k9 seg0 to 7 i lcdc controller/driver lcd segment output pin. p80 to p87 general purpose input/output port. 57 to 64 m10, l11, j9, m11, m12, k11, k10, l12 seg8 to 15 i lcdc controller/driver lcd segment output pin. p90 to p97 general purpose input/output port. 65 to 72 h9, j11, k12, j10, h11, j12, g9, h10 seg16 to 23 i lcdc controller/driver lcd segment output pin. pa0 to pa7 general purpose input/output port. 73, 74 h12, g11 seg24, 25 i lcdc controller/driver lcd segment output pin. pb0, pb1 general purpose input/output port. 75 g10 v cc ? power supply pin (i/o) 76 f11 v ss ? power supply pin (gnd) 77, 78 g12, f9 seg26, 27 i lcdc controller/driver lcd segment output pin. pb2, pb3 general purpose input/output port. 79 to 82 f10, e11, e9, d11 seg28 to 31 j lcdc controller/driver lcd segment output pin. p64 to p67 general purpose input/output port. (nch-od)
mb91230 series 10 (continued) pin no. pin name circuit type description lqfp flga 83 to 86 e10, d12, c11, d10 com0 to 3 i lcdc controller/driver common pins. p70 to p73 general purpose input/output port. 87 to 89 c12, b11, d9 mod2, 1, 0 h mode input pin. 90 b12 init g external reset input. 91 to 94 a12, b10, c10, a11 v0 to v3 ? lcd controller/driver reference power supply input pins. 95 d8 sin0 d uart0 data input. p00 general purpose input/output port. 96 b9 sot0 d uart0 data output. p01 general purpose input/output port. 97 a10 sck0 d uart0 clock input/output. p02 general purpose input/output port. 98 c9 sin1 d uart1 data input. p03 general purpose input/output port. 99 b8 sot1 d uart1 data output. p04 general purpose input/output port. 100 a9 sck1 d uart1 clock input/output. p05 general purpose input/output port. 101 d7 ic0 d input capture input 0. p06 general purpose input/output port. 102 c8 ic1 d input capture input 1. p07 general purpose input/output port. 103 a8 int0 a external interrupt input. p10 general purpose input/output port. 104 b7 int1 a external interrupt input. p11 general purpose input/output port. 105 c7 v cc ? power supply pin (i/o) 106 b6 v ss ? power supply pin (gnd) 107 a7 x1 ? main-clock oscillation pin 108 c6 x0 ? 109 a6 int2 a external interrupt input. p12 general purpose input/output port. 110 b5 int3 a external interrupt input. p13 general purpose input/output port.
mb91230 series 11 (continued) pin no. pin name circuit type description lqfp flga 111 d5 int4 a external interrupt input. p14 general purpose input/output port. 112 b4 int5 a external interrupt input. p15 general purpose input/output port. 113 c5 int6 a external interrupt input. p16 general purpose input/output port. 114 a4 int7 a external interrupt input. p17 general purpose input/output port. 115 b3 cki0 d external clock input pin for free-run timer 0. op0 output compare0 output pin. p20 general purpose input/output port. 116 c4 cki1 d external clock input pin for free-run timer 1. op1 output compare1 output pin. p21 general purpose input/output port. 117 a3 pwi0 d pulse width counter 0 input op2 output compare2 output pin. p22 general purpose input/output port. 118 b2 pwi1 d pulse width counter 0 input op3 output compare3 output pin. p23 general purpose input/output port. 119 d4 sin2 d uart2 data input. p24 general purpose input/output port. 120 a2 sot2 d uart2 data output. p25 general purpose input/output port.
mb91230 series 12 n n n n i/o circuit type (continued) type circuit type remarks a with pull-up control (50 k w ) cmos level output i oh = 4 ma/i ol = 4 ma cmos hysteresis input (with standby control) b with pull-up control (50 k w ) cmos level output i oh = 4 ma/i ol = 4 ma cmos hysteresis input (with standby control) test pin for flash c cmos level output cmos hysteresis input (with standby control) d cmos level output i oh = 4 ma/i ol = 4 ma cmos hysteresis input (with standby control) test pin for flash pp n pull-up control output drive pch output drive nch hysteresis input standby control pp n pull-up control output drive pch output drive nch hysteresis input standby control test pin for flash analog sw control p n output drive pch output drive nch hysteresis input standby control p n output drive pch output drive nch hysteresis input standby control test pin for flash analog sw control
mb91230 series 13 (continued) type circuit type remarks e cmos level output i oh = 4 ma/i ol = 4 ma cmos hysteresis input (with standby control) also serving as an analog input f cmos level output i oh = 4 ma/i ol = 4 ma cmos hysteresis input (with standby control) also serving as an analog input g with pull-up control (50 k w ) cmos hysteresis input h high withstand-voltage input cmos input (hysteresis level) p n output drive pch output drive nch hysteresis input standby control analog input analog sw control p n output drive pch output drive nch hysteresis input standby control analog input analog sw control p p n hysteresis input n n n n low impedance input high impedance input high voltage detection output
mb91230 series 14 (continued) type circuit type remarks i cmos level output i oh = 4 ma/i ol = 4 ma cmos hysteresis input (with standby control) lcdc output j cmos level output (open-drain) i ol = 20 ma cmos hysteresis input (with standby control) lcdc output k oscillation circuit p n output drive pch output drive nch hysteresis input standby control lcdc output p n output drive nch hysteresis input standby control lcdc output x1 x0 standby control oscillation output
mb91230 series 15 n n n n handling devices preventing latchup latch-up may occur in a cmos ic if a voltage greater than v cc or less than v ss is applied to an input or output pin or if an above-rating voltage is applied between v cc and v ss . a latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. when you use a cmos ic, be very careful not to exceed the maximum rating. treatment of unused pins do not leave an unused input pin open, since it may cause a malfunction. handle by, for example, using a pull- up or pull-down resistor. about power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. the power pins should be connected to v cc and v ss of this device at the lowest possible impedance from the current supply source. it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 m f between v cc and v ss near this device. about crystal oscillator circuit noise near the x0 and x1 pin may cause the device to malfunction. design the circuit board so that x0 and x1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended to design the pc board artwork with the x0 and x1 pins surrounded by ground plane because stable operation can be expected with such a layout. treatment of nc and open pins pins marked as nc or open must be left open-circuit. about mode pins (md0 to md2) these pins should be connected directly to v cc or v ss . to prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and v cc or v ss is as short as possible and the connection impedance is low. operation at start-up be sure to execute setting initialized reset (init) with init pin immediately after start-up. also, in order to provide a delay while the oscillator circuit stabilize immediately after start-up, maintain the l level input to the init pin for the required stabilization wait time. (for init via the init pin, the oscillation stabilization wait time setting is initialized to the minimum value) .
mb91230 series 16 about oscillation input at power on when turning the power on, maintain clock input untill the device is released from the oscillation stabilization wait state. clock control block input the l signal to the init pin to assure the clock oscillation stabilization wait time. switch shared port function to switch between the use as a port and the use as a dedicated pin, use the port function register (pfr) . low power consumption mode to enter the standby mode, use the synchronous standby mode (set with the syncs bit as bit 8 in the tbcr : timebse counter control register) and be sure to use the following sequence in addition, please set i flag, ilm, and icr to diverge to the interruption handler that is the return factor after the standby returns. ? please do not do the following when the monitor debugger is used. ? break point setting for above instruction lines ? step execution for above instruction lines power-on sequence for dual-power-supply model ? notes on the power-on and power-off sequences power-on sequence : vcc3b, vcc3 ? vcc ? vcc3io, avrh, v0-v3 power-off sequence : vcc3io, avrh, v0-v3 vcc3 ? vcc ? vcc3b, vcc3 when v cc is turned on earlier, a potential difference between v cc and v cc 3 must fall within 3.6 v. ? the lcd power supply v3 must not exceed v cc in voltage. apply v3 after turning on v cc 3. ? turn on v cc 3 before applying the analog power supply av cc or an analog signal. notes on the ps register as the ps register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the ps register to be updated. as the microcontroller is designed to carry out reprocessing correctly upon returning from such an eit event, it performs operations before and after the eit as specified in either case. (ldi #value_of_standby, r0) : value_of_standby is write data to stcr. (ldi #_stcr, r12) : _stcr is address (481h) of stcr. stb r0, @r12 : writing to standby control register (stcr) ldub @r12, r0 : stcr read for synchronous standby ldub @r12, r0 : dummy re-read of stcr nop : nop 5 for arrangement of timing nop nop nop nop
mb91230 series 17 ? the following operations may be performed when the instruction immediately followed by a divou/divos instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event or emulator menu : 1) the d0 and d1 flags are updated in advance. 2) an eit handling routine (user interrupt or emulator) is executed. 3) upon returning from the eit, the divou/divos instruction is executed, and the d0 and d1 flags are updated to the same values as in 1). ? the following operations are performed when the orccr/stilm/movri and ps instructions are executed. 1) the ps register is updated in advance. 2) an eit handling routine (user interrupt) is executed. 3) upon returning from the eit, the above instructions are executed, and the ps register is updated to the same value as in 1). watchdog timer the watchdog timer built in this model monitors a program that it defers a reset within a certain period of time. the watchdog timer resets the cpu if the program runs out of controls, preventing the reset defer function from being executed. once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on operating programs until it resets the cpu. as an exception, the watchdog timer defers a reset automatically under the condition in which the cpu stops program execution. for those conditions to which this exception applies, see the function description of watchdog timer. step execution of reti instruction if an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed repeatedly after step execution. this will prevent the main routine and low-interrupt-level programs from being executed. do not execute step of reti instruction for escape. disable the corresponding interrupt and execute debugger when the corresponding interrupt routine no longer needs debugging. operand break do not apply a data event break to access to the area containing the address of a system stack pointer.
mb91230 series 18 n n n n block diagram * : for shared ports, see pin description. r_bus d_bus i_bus f_bus 32 bits 32-bit fr60lite core delay interrupt watchdog timer rom : 256 kb (flash : 256 kb) ram : 16 kb (eva : 24 kb) 32-bit 16-bit bus converter bit serch module harverd princeton bus converter interrupt a/d0 (an0, 1, 2, 3) a/d1 (an4, 5, 6, 7) d/a0 d/a 1 rtc pwc0 pwc1 clock monitor external interrupt lcdc ports r_bus 16-bit x0/1 x0a/1a clock, standby, reset, watchdog, (tbt) u-timer 0 uart0 (r) uart0 (t) u-timer 1 uart1 (r) uart1 (t) u-timer 2 uart2 (r) uart2 (t) u-timer 3 oc0, oc1 free-run timer 0 ic0 ic1 free-run timer 1 oc2, oc3 reload timer 0 reload timer 1 reload timer 2 reload timer 3 ppg0 ppg1 ppg2 ppg3 ppg4 ppg5 ud counter 0 ud counter 1 uart3 (r) uart3 (t)
mb91230 series 19 n n n n memory space 1. memory space the fr60 lite family has 4 gigabytes of logical address space (2 32 addresses) available to the cpu by linear access. ? direct addressing areas the following address space areas are used as i/o areas. these areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. the size of directly addressable areas depends on the length of the data being accessed as shown below. byte data access : 0 to 0ff h half word data access : 0 to 1ff h word data access : 0 to 3ff h 2. memory map note : do not set the external bus mode in which the mb91230 series cannot operate. 0000 0000 h 0000 0400 h 0001 0000 h 0003 a000 h 0004 0000 h 0008 0000 h 0010 0000 h ffff ffff h 0001 0000 h 0003 c000 h 0004 0000 h 000c 0000 h 0010 0000 h ffff ffff h i/o i/o i/o mb91v230 mb91f233/l, mb91233l i/o direct addressing areas access disallowed refer to i/o map access disallowed built-in ram 24 kb access disallowed emulation sram area 512 kb access disallowed built-in ram 16 kb access disallowed built-in flash rom 256 kb access disallowed
mb91230 series 20 n n n n mode settings the fr family uses mode pins (md2 to md0) and a mode data to set the operation mode. ? mode pins the md2, md1, and md0 pins specify how the mode vector fetch and reset vector fetch is performed. setting is prohibited other than that shown in the following table. ? mode data data written to the internal mode register (modr) by a mode vector fetch (see reset sequence) is called mode data. after an operation mode has been set in the mode register, the device operates in the operation mode. the mode data is set by all reset source. user programs cannot set data to the mode register. details of mode data description [bit31 to bit27] reserved bit be sure to set this bit to 00000. operation is not guaranteed when any value other than 00000 is set. [bit26] roma : internal rom enable bit specifies whether the internal rom area is enabled. for this model, be sure to set 1. [bit25, bit24] wth1, wth0 (bus width setting bits) this sets the bus width in external bus mode. in external bus mode, the values of bits dbw1 and dbw0 in acr0 (cs0 area) are set in these bits. for this model, be sure to set 11 mode pins mode name reset vector access area remarks md2 md1 md0 0 0 0 internal rom mode vector internal 0 0 1 external rom mode vector external not supported by this model. roma function remarks 0 external rom mode not supported by this model. 1 internal rom mode the internal rom area is enabled. wth1 wth0 function remarks 0 0 8-bit bus width not supported by this model. 0 1 16 - bit bus width not supported by this model. 10 ? 1 1 single chip mode 31 bit 30 29 28 27 26 25 24 0 0 0 0 0 roma wth1 wth1 operation mode setting bits
mb91230 series 21 note : mode data set in the mode vector must be placed as byte data at 0x000ffff8 h . use the highest byte from bit31 to bit24 for placement as the fr family uses the big endian for byte endian. 31 bit 24 23 16 15 8 7 0 xxxxxxxx 0x000ffff8 h 0x000ffff8 h 0x000ffffc h xxxxxxxx xxxxxxxx mode data mode data reset vector xxxxxxxx xxxxxxxx xxxxxxxx incorrect correct
mb91230 series 22 ? operation mode ? bus mode bus mode indicates the mode that controls the internal rom operations and external access function operations, and specifies using the mode set up terminals (md2, md1 and md0) and roma bit contents within the mode data. ? access mode access mode indicates the mode that controls the external data bus width, and specifies by the wth1/wth0 bits within the mode data, and the dbw1/dbw0 bits within acr0 to acr3 (area configuration registers) . ? bus mode in the fr60 lite, there are 3 bus modes shown next. refer to n memory space for details. ? bus mode 0 (single chip mode) this mode enables access to internal i/o, external ram, and to internal rom while disabling access to any other area. the external pin functions as a peripheral function or a general purpose port. the pin does not work as a bus pin. ? bus mode 1 (internal rom external bus mode) not supported by this model. this mode enables access to internal i/o, internal ram, and to internal rom, in which access to externally accessible areas are handled as access to external space. a part of an external pin functions as a bus pin. ? bus mode 2 (external rom external bus mode) not supported by this model. this mode enables access to internal i/o and internal ram while disabling access to internal rom, in which access to externally accessible areas or internal rom space are handled as access to external space. a part of an external functions as a bus pin. bus mode access mode single chip internal rom external bus external rom external bus 16-bit bus width 8-bit bus width
mb91230 series 23 n n n n i/o map [how to read the table] note : initial values of register bits are represented as follows : 1 : initial value 1 0 : initial value 0 x : initial value undefined - : no physical register at this location access is barred with an undefined data access attribute. address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000000 h pdr0 [r/w] xxxxxxxx pdr1 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx pdr3 [r/w] xxxxxxxx t-unit port data register data access attribute (b : byte, h : half word, w : word) read/write attribute (r : read, w : write) register name (first-column register at address 4n; second-column register at address 4n + 2) location of left-most register (when using word access, the register in column 1 is in the msb side of the data.)
mb91230 series 24 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000000 h pdr0 [r/w] b xxxxxxxx pdr1 [r/w] b xxxxxxxx pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx port data register 000004 h pdr4 [r/w] b xxxxxxxx pdr5 [r/w] b xxxxxxxx pdr6 [r/w] b xxxx---- pdr7 [r/w] b ----xxxx 000008 h pdr8 [r/w] b xxxxxxxx pdr9 [r/w] b xxxxxxxx pdra [r/w] b xxxxxxxx pdrb [r/w] b ----xxxx 00000c h pdrc [r/w] b xxxxxxxx pdrd [r/w] b ------xx ? pdrf [r/w] ---xx--- 000010 h to 00003c h ???? unused 000040 h eirr0 [r/w] b, h, w 00000000 enir0 [r/w] b, h, w 00000000 elvr0 [r/w] b, h, w 00000000 00000000 external interrupt (int0 to 7) 000044 h dicr [r/w] b, h, w -------0 ?? delay interrupt 000048 h tmrlr0 [w] h, w xxxxxxxx xxxxxxxx tmr0 [r] h, w xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r/w] b, h, w ----0000 00000000 000050 h tmrlr1 [w] h, w xxxxxxxx xxxxxxxx tmr1 [r] h, w xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r/w] b, h, w ----0000 00000000 000058 h tmrlr2 [w] h, w xxxxxxxx xxxxxxxx tmr2 [r] h, w xxxxxxxx xxxxxxxx reload timer 2 00005c h ? tmcsr2 [r/w] b, h, w ----0000 00000000 000060 h ssr0 [r/w] b, h, w 00001000 sidr0 [r] b, h, w sodr0 [w] b, h, w xxxxxxxx scr0 [r/w] b, h, w 00000100 smr0 [r/w] b, h, w 00--0-0- uart0 000064 h utim0 [r] h (utimr0 [w] h) 00000000 00000000 ? utimc0 [r/w] b 0--00001 u-timer0 000068 h ssr1 [r/w] b, h, w 00001000 sidr1 [r] b, h, w sodr1 [w] b, h, w xxxxxxxx scr1 [r/w] b, h, w 00000100 smr1 [r/w] b, h, w 00--0-0- uart1 00006c h utim1 [r] h (utimr1 [w] h) 00000000 00000000 ? utimc1 [r/w] b 0--00001 u-timer1
mb91230 series 25 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000070 h ssr2 [r/w] b, h, w 00001000 sidr2 [r] b, h, w sodr2 [w] b, h, w xxxxxxxx scr2 [r/w] b, h, w 00000100 smr2 [r/w] b, h, w 00--0-0- uart2 000074 h utim2 [r] h (utimr1 [w] h) 00000000 00000000 ? utimc2 [r/w] b 0--00001 u-timer2 000078 h adcs0 [r/w] h, w xxxxxxxx xxxxxxxx adct0 [r/w] h, w 000-0000 -000--00 a/d converter 0 (series-parallel type) 00007c h adt00 (adth0/adtl0) [r] h, w 000000xx xxxxxxxx adt01 (adth1/adtl1) [r] h, w 000000xx xxxxxxxx 000080 h adt02 (adth2/adtl2) [r] h, w 000000xx xxxxxxxx adt03 (adth3/adtl3) [r] h, w 000000xx xxxxxxxx 000084 h adcs1 [r/w] h, w xxxxxxxx xxxxxxxx adct1 [r/w] h, w 000-0000 --000--00 a/d converter 1 (series-parallel type) 000088 h adt10 (adth0/adtl0) [r] h, w 000000xx xxxxxxxx adt11 (adth1/adtl1) [r] h, w 000000xx xxxxxxxx 00008c h adt12 (adth2/adtl2) [r] h, w 000000xx xxxxxxxx adt13 (adth3/adtl3) [r] h, w 000000xx xxxxxxxx 000090 h ?? dacr1 [r/w] b, h, w -------0 dacr0 [r/w] b, h, w -------0 d/a converter 000094 h ?? dadr1 [r/w] b, h, w xxxxxxxx dadr0 [r/w] b, h, w xxxxxxxx 000098 h lcdcmr [r/w] b, h, w ----0000 ? lcr0 [r/w] b, h, w 00010000 lcr1 [r/w] b, h, w 00000000 lcd controller/driver 00009c h vram0 [r/w] b, h, w xxxxxxxx vram1 [r/w] b, h, w xxxxxxxx vram2 [r/w] b, h, w xxxxxxxx vram3 [r/w] b, h, w xxxxxxxx 0000a0 h vram4 [r/w] b, h, w xxxxxxxx vram5 [r/w] b, h, w xxxxxxxx vram6 [r/w] b, h, w xxxxxxxx vram7 [r/w] b, h, w xxxxxxxx 0000a4 h vram8 [r/w] b, h, w xxxxxxxx vram9 [r/w] b, h, w xxxxxxxx vram10 [r/w] b, h, w xxxxxxxx vram11 [r/w] b, h, w xxxxxxxx 0000a8 h vram12 [r/w] b, h, w xxxxxxxx vram13 [r/w] b, h, w xxxxxxxx vram14 [r/w] b, h, w xxxxxxxx vram15 [r/w] b, h, w xxxxxxxx 0000ac h ckr [r/w] b, h, w ----0000 ??? clock monitor
mb91230 series 26 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 0000b0 h rcr1 [w] b, h, w 00000000 rcr0 [w] b, h, w 00000000 udcr1 [r] b, h, w 00000000 udcr0 [r] b, h, w 00000000 up/down counter0, 1 0000b4 h ccrh0 [r/w] b, h, w 00000000 ccrl0 [r/w] b, h, w 00001000 ? csr0 [r/w] b, h, w 00000000 0000b8 h ccrh1 [r/w] b, h, w 00000000 ccrl1 [r/w] b, h, w 00001000 ? csr1 [r/w] b, h, w 00000000 0000bc h ???? unused 0000c0 h ssr [r/w] b, h, w 00001000 sidr 3 [r] b, h, w sodr 3 [w] b, h, w xxxxxxxx scr [r/w] b, h, w 00000100 smr [r/w] b, h, w 00--0-0- uart3 0000c4 h utim [r] h (utimr [w] h) 00000000 00000000 ? utimc [r/w] b 0--00001 u-timer3 0000c8 h tmrlr3 [w] h, w xxxxxxxx xxxxxxxx tmr3 [r] h, w xxxxxxxx xxxxxxxx reload timer 3 0000cc h ? tmcsr3 [r/w] b, h, w ---00000 00000000 0000d0 h eirr1 [r/w] b, h, w 00000000 enir1 [r/w] b, h, w 00000000 elvr1 [r/w] b, h, w 00000000 00000000 external interrupt (int8 to 16) 0000d4 h tcdt0 [r/w] h, w 00000000 00000000 ? tccs0 [r/w] b, h, w 00000000 free-run timer 0 0000d8 h tcdt1 [r/w] h, w 00000000 00000000 ? tccs1 [r/w] b, h, w 00000000 free-run timer 1 0000dc h ipcp1 [r] h, w xxxxxxxx xxxxxxxx ipcp0 [r] h, w xxxxxxxx xxxxxxxx input capture 0000e0 h ??? ics01 [r/w] b, h, w 00000000 0000e4 h occp1 [r/w] h, w xxxxxxxx xxxxxxxx occp0 [r/w] h, w xxxxxxxx xxxxxxxx output compare 0000e8 h occp3 [r/w] h, w xxxxxxxx xxxxxxxx occp2 [r/w] h, w xxxxxxxx xxxxxxxx 0000ec h ocs23 [r/w] b, h, w ---0--00 0000--00 ocs01 [r/w] b, h, w ---0-00 0000--00
mb91230 series 27 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 0000f0 h pwcc0 [r/w] b, h, w 0---00-0 pwcd0 [r] b, h, w xxxxxxxx pwcc1 [r/w] b, h, w 0---00-0 pwcd1 [r] b, h, w xxxxxxxx pwc0, 1 0000f4 h ? wtdbl [r/w] b -------0 wtcr [r/w] b, h 00000000 000-00-x real-time clock 0000f8 h ? wtbr0 [r/w] b ---xxxxx wtbr1 [r/w] b xxxxxxxx wtbr2 [r/w] b xxxxxxxx 0000fc h wthr [r/w] b, h ---xxxxx wtmr [r/w] b, h --xxxxxx wtsr [r/w] b --xxxxxx ? 000100 h to 000114 h ???? unused 000118 h gcn10 [r/w] h 00110010 00010000 ? gcn20 [r/w] b 00000000 ppg 00011c h ?? unused 000120 h ptmr0 [r] h, w 11111111 11111111 pcsr0 [w] h, w xxxxxxxx xxxxxxxx ppg0 000124 h pdut0 [w] h, w xxxxxxxx xxxxxxxx pcnh0 [r/w] b, h, w 00000000 pcnl0 [r/w] b, h, w 00000000 000128 h ptmr1 [r] h, w 11111111 11111111 pcsr1 [w] h, w xxxxxxxx xxxxxxxx ppg1 00012c h pdut1 [w] h, w xxxxxxxx xxxxxxxx pcnh1 [r/w] b, h, w 00000000 pcnl1 [r/w] b, h, w 00000000 000130 h ptmr2 [r] h, w 11111111 11111111 pcsr2 [w] h, w xxxxxxxx xxxxxxxx ppg2 000134 h pdut2 [w] h, w xxxxxxxx xxxxxxxx pcnh2 [r/w] b, h, w 00000000 pcnl2 [r/w] b, h, w 00000000 000138 h ptmr3 [r] h, w 11111111 11111111 pcsr3 [w] h, w xxxxxxxx xxxxxxxx ppg3 00013c h pdut3 [w] h, w xxxxxxxx xxxxxxxx pcnh3 [r/w] b, h, w 00000000 pcnl3 [r/w] b, h, w 00000000 000140 h ptmr4 [r] h, w 11111111 11111111 pcsr4 [w] h, w xxxxxxxx xxxxxxxx ppg4 000144 h pdut4 [w] h, w xxxxxxxx xxxxxxxx pcnh4 [r/w] b, h, w 00000000 pcnl4 [r/w] b, h, w 00000000
mb91230 series 28 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000148 h ptmr5 [r] h, w 11111111 11111111 pcsr5 [w] h, w xxxxxxxx xxxxxxxx ppg5 00014c h pdut5 [w] h, w xxxxxxxx xxxxxxxx pcnh5 [r/w] b, h, w 00000000 pcnl5 [r/w] b, h, w 00000000 000150 h to 0001fc h ???? unused 000200 h to 0003ec h ???? unused 0003f0 h bsd0 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search 0003f4 h bsd1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddr0 [r/w] b 00000000 ddr1 [r/w] b 00000000 ddr2 [r/w] b 00000000 ddr3 [r/w] b00000000 data direction register 000404 h ddr4 [r/w] b 00000000 ddr5 [r/w] b 00000000 ddr6 [r/w] b 0000---- ddr7 [r/w] b ----0000 000408 h ddr8 [r/w] b 00000000 ddr9 [r/w] b 00000000 ddra [r/w] b 00000000 ddrb [r/w] b ----0000 00040c h ddrc [r/w] b 00000000 ddrd [r/w] b ------00 ? ddrf [r/w] b ---00--- 000410 h to 00041c h ???? unused 000420 h pfr0 [r/w] b --00-00- pfr1 [r/w] b -------- pfr2 [r/w] b -00-0000 pfr3 [r/w] b ------00 port function register 000424 h pfr4 [r/w] b 00000000 pfr5 [r/w] b ---00--- pfr6 [r/w] b 0000---- pfr7 [r/w] b ----0000 000428 h pfr8 [r/w] b 00000000 pfr9 [r/w] b 00000000 pfra [r/w] b 00000000 pfrb [r/w] b ----0000 00042c h pfrc [r/w] b -------- pfrd [r/w] b ------00 ? pfrf [r/w] b ----0--- 000430 h to 00043c h ???? unused
mb91230 series 29 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000440 h icr00 [r/w] b, h, w ---11111 icr01 [r/w] b, h, w ---11111 icr02 [r/w] b, h, w ---11111 icr03 [r/w] b, h, w ---11111 interrupt control unit 000444 h icr04 [r/w] b, h, w ---11111 icr05 [r/w] b, h, w ---11111 icr06 [r/w] b, h, w ---11111 icr07 [r/w] b, h, w ---11111 000448 h icr08 [r/w] b, h, w ---11111 icr09 [r/w] b, h, w ---11111 icr10 [r/w] b, h, w ---11111 icr11 [r/w] b, h, w ---11111 00044c h icr12 [r/w] b, h, w ---11111 icr13 [r/w] b, h, w ---11111 icr14 [r/w] b, h, w ---11111 icr15 [r/w] b, h, w ---11111 000450 h icr16 [r/w] b, h, w ---11111 icr17 [r/w] b, h, w ---11111 icr18 [r/w] b, h, w ---11111 icr19 [r/w] b, h, w ---11111 000454 h icr20 [r/w] b, h, w ---11111 icr21 [r/w] b, h, w ---11111 icr22 [r/w] b, h, w ---11111 icr23 [r/w] b, h, w ---11111 000458 h icr24 [r/w] b, h, w ---11111 icr25 [r/w] b, h, w ---11111 icr26 [r/w] b, h, w ---11111 icr27 [r/w] b, h, w ---11111 00045c h icr28 [r/w] b, h, w ---11111 icr29 [r/w] b, h, w ---11111 icr30 [r/w] b, h, w ---11111 icr31 [r/w] b, h, w ---11111 000460 h icr32 [r/w] b, h, w ---11111 icr33 [r/w] b, h, w ---11111 icr34 [r/w] b, h, w ---11111 icr35 [r/w] b, h, w ---11111 000464 h icr36 [r/w] b, h, w ---11111 icr37 [r/w] b, h, w ---11111 icr38 [r/w] b, h, w ---11111 icr39 [r/w] b, h, w ---11111 000468 h icr40 [r/w] b, h, w ---11111 icr41 [r/w] b, h, w ---11111 icr42 [r/w] b, h, w ---11111 icr43 [r/w] b, h, w ---11111 00046c h icr44 [r/w] b, h, w ---11111 icr45 [r/w] b, h, w ---11111 icr46 [r/w] b, h, w ---11111 icr47 [r/w] b, h, w ---11111 000470 h to 00047c h ???? unused
mb91230 series 30 (continued) * : this register is set when the mode vector is fetched. not user-accessible. address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000480 h rsrr [r/w] b, h, w 10000000 stcr [r/w] b, h, w 00110011 tbcr [r/w] b, h, w 00xxxx00 ctbr [w] b, h, w xxxxxxxx clock control 000484 h clkr [r/w] b, h, w 00000000 wpr [r/w] b, h, w xxxxxxxx divr0 [r/w] b, h, w 00000011 divr1 [r/w] b, h, w 00000000 000488 h ?? osccr [r/w] b xxxxxxx0 ? 00048c h wpcr [r/w] b 00---000 ??? watch timer 000490 h oscr [r/w] b 00---000 ??? main clock oscillation stabilization wait timer 000494 h to 0004fc h ???? unused 000500 h ? pcr1 [r/w] b 00000000 ? pcr3 [r/w] b 00000000 pull-up control register 000504 h to 00051c h ???? unused 000520 h to 0007f8 h ???? unused 0007fc h ? modr* xxxxxxxx ?? operation mode 000800 h to 000afc h ???? unused 000b00 h to 000ffc h ???? unused 001000 h to 001ffc h ???? unused
mb91230 series 31 n n n n interrupt vector (continued) interrupt source interrupt number interrupt level offset tbr default address 10 16 reset 0 00 ? 3fc h 000ffffc h mode vector 1 01 ? 3f8 h 000ffff8 h system reserved 2 02 ? 3f4 h 000ffff4 h system reserved 3 03 ? 3f0 h 000ffff0 h system reserved 4 04 ? 3ec h 000fffec h system reserved 5 05 ? 3e8 h 000fffe8 h system reserved 6 06 ? 3e4 h 000fffe4 h coprocessor absent trap 7 07 ? 3e0 h 000fffe0 h coprocessor error trap 8 08 ? 3dc h 000fffdc h inte instruction 9 09 ? 3d8 h 000fffd8 h instruction break exception 10 0a ? 3d4 h 000fffd4 h operand break trap 11 0b ? 3c0 h 000fffd0 h step trace trap 12 0c ? 3cc h 000fffcc h nmi request (tool) 13 0d ? 3c8 h 000fffc8 h undefined instruction exception 14 0e ? 3c4 h 000fffc4 h nmi request (this model has no nmi request) 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h external interrupt 0 16 10 icr00 3bc h 000fffbc h external interrupt 1 17 11 icr01 3b8 h 000fffb8 h external interrupt 2 18 12 icr02 3b4 h 000fffb4 h external interrupt 3 19 13 icr03 3b0 h 000fffb0 h external interrupt 4 20 14 icr04 3ac h 000fffac h external interrupt 5 21 15 icr05 3a8 h 000fffa8 h external interrupt 6 22 16 icr06 3a4 h 000fffa4 h external interrupt 7 23 17 icr07 3a0 h 000fffa0 h reload timer 0 24 18 icr08 39c h 000fff9c h reload timer 1 25 19 icr09 398 h 000fff98 h reload timer 2 26 1a icr10 394 h 000fff94 h uart0(reception completed) 27 1b icr11 390 h 000fff90 h uart0 (transmission completed) 28 1c icr12 38c h 000fff8c h uart1 (reception completed) 29 1d icr13 388 h 000fff88 h uart1 (transmission completed) 30 1e icr14 384 h 000fff84 h uart2 (reception completed) 31 1f icr15 380 h 000fff80 h uart2 (transmission completed) 32 20 icr16 37c h 000fff7c h
mb91230 series 32 (continued) interrupt source interrupt number interrupt level offset tbr default address 10 16 uart3 (reception completed) 33 21 icr17 378 h 000fff78 h uart3 (transmission completed) 34 22 icr18 374 h 000fff74 h a/d ch0 35 23 icr19 370 h 000fff70 h a/d ch1 36 24 icr20 36c h 000fff6c h external interrupt8 37 25 icr21 368 h 000fff68 h external interrupt9 38 26 icr22 364 h 000fff64 h external interrupt 10 39 27 icr23 360 h 000fff60 h external interrupt 11 40 28 icr24 35c h 000fff5c h external interrupt 12 41 29 icr25 358 h 000fff58 h external interrupt 13 42 2a icr26 354 h 000fff54 h external interrupt 14 43 2b icr27 350 h 000fff50 h external interrupt 15 44 2c icr28 34c h 000fff4c h real-time clock 45 2d icr29 348 h 000fff48 h main clock oscillation stabilization wait timer 46 2e icr30 344 h 000fff44 h timebase timer 0 overflow 47 2f icr31 340 h 000fff40 h reload timer 3 48 30 icr32 33c h 000fff3c h watch timer 49 31 icr33 338 h 000fff38 h ud counter 0 50 32 icr34 334 h 000fff34 h ud counter 1 51 33 icr35 330 h 000fff30 h ppg 0/1 52 34 icr36 32c h 000fff2c h ppg 2/3 53 35 icr37 328 h 000fff28 h ppg 4/5 54 36 icr38 324 h 000fff24 h free-run timer 0 55 37 icr39 320 h 000fff20 h free-run timer 1 56 38 icr40 31c h 000fff1c h icu 0 (capture) 57 39 icr41 318 h 000fff18 h icu 1 (capture) 58 3a icr42 314 h 000fff14 h ocu 0 (match) 59 3b icr43 310 h 000fff10 h ocu 1 (match) 60 3c icr44 30c h 000fff0c h ocu 2 (match) 61 3d icr45 308 h 000fff08 h ocu 3 (match) 62 3e icr46 304 h 000fff04 h delay interrupt source bit 63 3f icr47 300 h 000fff00 h system reserved (used by realos) 64 40 ? 2fc h 000ffefc h system reserved (used by realos) 65 41 ? 2f8 h 000ffef8 h system reserved 66 42 ? 2f4 h 000ffef4 h
mb91230 series 33 (continued) interrupt source interrupt number interrupt level offset tbr default address 10 16 system reserved 67 43 ? 2f0 h 000ffef0 h system reserved 68 44 ? 2ec h 000ffeec h system reserved 69 45 ? 2e8 h 000ffee8 h system reserved 70 46 ? 2e4 h 000ffee4 h system reserved 71 47 ? 2e0 h 000ffee0 h system reserved 72 48 ? 2dc h 000ffedc h system reserved 73 49 ? 2d8 h 000ffed8 h system reserved 74 4a ? 2d4 h 000ffed4 h system reserved 75 4b ? 2d0 h 000ffed0 h system reserved 76 4c ? 2cc h 000ffecc h system reserved 77 4d ? 2c8 h 000ffec8 h system reserved 78 4e ? 2c4 h 000ffec4 h system reserved 79 4f ? 2c0 h 000ffec0 h used by int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h
mb91230 series 34 n n n n pin status in each cpu state terms used as the status of pins mean as follows. ? input enabled indicates that the input function can be used. ? input 0 fixed indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released. ? output hi-z means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving. ? output is maintained indicates the output in the output state existing immediately before this mode is established. if the device enters this mode with an internal output peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. ? state existing immediately before is maintained when the device serves for output or input immediately before entering this mode, the device maintains the output or is ready for the input, respectively.
mb91230 series 35 ~ pin status list (continued) pin no. pin name port name specified function name at initializing at sleep mode at stop mode remarks input output input/ output function name reset initializa- tion hiz = = = = 0 hiz = = = = 1 1 p26/ sck2 p26 ?? sck2 p26 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 2 p27/ sin3 p27 sin3 ?? p27 3 p30/ sot3 p30 ? sot3 ? p30 pull-up options can be selected 4 p31/ sck3 p31 ?? sck3 p31 pull-up options can be selected 5 p32/ ain0 p32 ain0 ?? p32 pull-up options can be selected 6 p33/ bin0 p33 bin0 ?? p33 pull-up options can be selected 7 p34/ zin0 p34 zin0 ?? p34 pull-up options can be selected 8 p35/ ain1 p35 ain1 ?? p35 pull-up options can be selected 9 p36/ bin1 p36 bin1 ?? p36 pull-up options can be selected 10 p37/ zin1 p37 zin1 ?? p37 pull-up options can be selected 11 p40/ ppg0 p40 ? ppg 0 ? p40 12 p41/ ppg1 p41 ? ppg 1 ? p41
mb91230 series 36 p : port selected, f : specified function selected (continued) pin no. pin name port name specified function name at initializing at sleep mode at stop mode remarks input output input/ output function name reset initialization hiz = = = = 0 hiz = = = = 1 13 x0a 14 x1a 15 v cc 3b/ v cc 16 v ss 17 v cc 3/c 18 p42/ ppg2 p42 ? ppg2 ? p42 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 19 p43/ ppg3 p43 ? ppg3 ? p43 20 p44/ tot0 p44 ? tot0 ? p44 21 p45/ tot1 p45 ? tot1 ? p45 22 p46/ tot2 p46 ? tot2 ? p46 23 p47/ ckot p47 ? ckot ? p47 24 p50/ int8 p50 int8 ?? p50 p : retention of the immediately prior state f : input enabled p : output hi-z f : input enabled 25 p51/ int9 p51 int9 ?? p51 26 p52/ int10 p52 int10 ?? p52 27 p53/ int11/ ppg4 p53 int11 ppg4 ? p53 28 p54/ int12/ ppg5 p54 int12 ppg5 ? p54 29 p55/ int13/ tin2 p55 int13 tin2 ?? p55 30 p56/ int14/ tin1 p56 int14 tin1 ?? p56
mb91230 series 37 p : port selected, f : specified function selected (continued) pin no. pin name port name specified function name at initializing at sleep mode at stop mode remarks input output input/ output function name reset initialization hiz = = = = 0hiz = = = = 1 31 p57/ int15/ tin0/ adtg0 p57 int15 tin0 adtg0 ?? p57 output hi-z/ input enabled retention of the immediately prior state p : retention of the immediately prior state f : input enabled p : output hi-z/ f : input 0 enabled 32 pf3/ tot3 pf3 ? tot3 ? pf3 retention of the immediately prior state output hi-z/ input 0 fixed 33 pf4/ tin3/ adtg1 pf4 tin3 adtg1 ?? pf4 34 pd0/ da0 pd0 ? da0 ? pd0 35 pd1/ da1 pd1 ? da1 ? pd1 36 av cc 37 avrh 38 av ss 39 pc0/ an0 pc0 an0 ?? pc0 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 40 pc1/ an1 pc1 an1 ?? pc1 41 pc2/ an2 pc2 an2 ?? pc2 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 42 pc3/ an3 pc3 an3 ?? pc3 43 pc4/ an4 pc4 an4 ?? pc4 44 pc5/ an5 pc5 an5 ?? pc5 45 pc6/ an6 pc6 an6 ?? pc6 46 pc7/ an7 pc7 an7 ?? pc7
mb91230 series 38 p : port selected, f : specified function selected (continued) pin no. pin name port name specified function name at initializing at sleep mode at stop mode remarks input output input/ output function name reset initialization hiz = = = = 0hiz = = = = 1 47 v ss 48 v cc 3io 49 p80/ seg0 p80 ? seg0 ? p80 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state p(port) : output hi-z/ input 0 fixed f (peripheral) : retention of the immediately prior state 50 p81/ seg1 p81 ? seg1 ? p81 51 p82/ seg2 p82 ? seg2 ? p82 52 p83/ seg3 p83 ? seg3 ? p83 53 p84/ seg4 p84 ? seg4 ? p84 54 p85/ seg5 p85 ? seg5 ? p85 55 p86/ seg6 p86 ? seg6 ? p86 56 p87/ seg7 p87 ? seg7 ? p87 57 p90/ seg8 p90 ? seg8 ? p90 58 p91/ seg9 p91 ? seg9 ? p91 59 p92/ seg10 p92 ? seg10 ? p92 60 p93/ seg11 p93 ? seg11 ? p93 61 p94/ seg12 p94 ? seg12 ? p94 62 p95/ seg13 p95 ? seg13 ? p95 63 p96/ seg14 p96 ? seg14 ? p96
mb91230 series 39 p : port selected, f : specified function selected (continued) pin no. pin name port name specified function name at initializing at sleep mode at stop mode remarks input output input/ output function name reset initialization hiz = = = = 0 hiz = = = = 1 64 p97/ seg15 p97 ? seg15 ? p97 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state p(port) : output hi-z/ input 0 fixed f (peripheral) : retention of the immediately prior state 65 pa0/ seg16 pa0 ? seg16 ? pa0 66 pa1/ seg17 pa1 ? seg17 ? pa1 67 pa2/ seg18 pa2 ? seg18 ? pa2 68 pa3/ seg19 pa3 ? seg19 ? pa3 69 pa4/ seg20 pa4 ? seg20 ? pa4 70 pa5/ seg21 pa5 ? seg21 ? pa5 71 pa6/ seg22 pa6 ? seg22 ? pa6 72 pa7/ seg23 pa7 ? seg23 ? pa7 73 pb0/ seg24 pb0 ? seg24 ? pb0 74 pb1/ seg25 pb1 ? seg25 ? pb1 75 v cc 76 v ss 77 pb2/ seg26 pb2 ? seg26 ? pb2 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state p(port) : output hi-z/ input 0 fixed f (peripheral) : retention of the immediately prior state 78 pb3/ seg27 pb3 ? seg27 ? pb3 79 p64/ seg28 * p64 ? seg28 ? p64 pseudo nch-od pin, iol = 20ma
mb91230 series 40 p : port selected, f : specified function selected (continued) pin no. pin name port name specified function name at initializing at sleep mode at stop mode remarks input output input/ output function name reset initialization hiz = = = = 0hiz = = = = 1 80 p65/ seg29 * p65 ? seg29 ? p65 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state p(port) : output hi-z/ input 0 fixed f (peripheral) : retention of the immediately prior state pseudo nch-od pin, iol = 20ma 81 p66/ seg30 * p66 ? seg30 ? p66 pseudo nch-od pin, iol = 20ma 82 p67/ seg31 * p67 ? seg31 ? p67 pseudo nch-od pin, iol = 20ma 83 p70/ com0 p70 ? com0 ? p70 84 p71/ com1 p71 ? com1 ? p71 85 p72/ com2 p72 ? com2 ? p72 86 p73/ com3 p73 ? com3 ? p73 87 mod2 88 mod1 89 mod0 90 init 91 v0 92 v1 93 v2 94 v3
mb91230 series 41 p : port selected, f : specified function selected (continued) pin no. pin name port name specified function name at initializing at sleep mode at stop mode remarks input output input/ output function name reset initialization hiz = = = = 0 hiz = = = = 1 95 p00/ sin0 p00 sin0 ?? p00 output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 96 p01/ sot0 p01 ? sot0 ? p01 97 p02/ sck0 p02 ?? sck0 p02 98 p03/ sin1 p03 sin1 ?? p03 99 p04/ sot1 p04 ? sot1 ? p04 100 p05/ sck1 p05 ?? sck1 p05 101 p06/ ic0 p06 ic0 ?? p06 102 p07/ ic1 p07 ic1 ?? p07 103 p10/ int0 p10 int0 ?? p10 p : retention of the immediately prior state f : input enabled p : output hi-z f : input enabled pull-up options can be selected 104 p11/ int1 p11 int1 ?? p11 pull-up options can be selected 105 v cc 106 v ss 107 x1 108 x0
mb91230 series 42 (continued) p : port selected, f : specified function selected pin no. pin name port name specified function name at initializing at sleep mode at stop mode remarks input output input/ output function name reset initialization hiz = = = = 0 hiz = = = = 1 109 p12/ int2 p12 int2 ?? p12 output hi-z/ input enabled retention of the immediately prior state p : retention of the immediately prior state f : input enabled p : output hi-z f : input enabled pull-up options can be selected 110 p13/ int3 p13 int3 ?? p13 pull-up options can be selected 111 p14/ int4 p14 int4 ?? p14 pull-up options can be selected 112 p15/ int5 p15 int5 ?? p15 pull-up options can be selected 113 p16/ int6 p16 int6 ?? p16 pull-up options can be selected 114 p17/ int7 p17 int7 ?? p17 pull-up options can be selected 115 p20/ cki0/ op0 p20 cki0 op0 ? p20 retention of the immediately prior state output hi-z/ input 0 fixed 116 p21/ cki1/ op1 p21 cki1 op1 ? p21 117 p22/ pwi0/ op2 p22 pwi0 op2 ? p22 118 p23/ pwi1/ op3 p23 pwi1 op3 ? p23 119 p24/ sin2 p24 sin2 ?? p24 120 p25/ sot2 p25 ? sot2 ? p25
mb91230 series 43 n n n n electrical characteristics 1. absolute maximum ratings mb91f233, mb91v230 mb91f233l, mb91233l warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage vcc v ss - 0.5 v ss + 6.0 v vcc3 v ss - 0.5 v ss + 4.0 v vcc3io v ss - 0.5 v ss + 4.0 v analog power supply voltage avcc v ss - 0.5 v ss + 4.0 v input voltage vi v ss - 0.5 v cc + 0.5 v input voltage (nch-od) vind v ss - 0.5 v cc + 0.5 v analog pin input voltage via v ss - 0.5 av cc + 0.5 v output voltage vo v ss - 0.5 v cc + 0.5 v storage temperature tstg - 55 + 125 c parameter symbol rating unit remarks min max power supply voltage vcc v ss - 0.5 v ss + 4.0 v vcc3 v ss - 0.5 v ss + 4.0 v vcc3io v ss - 0.5 v ss + 4.0 v analog power supply voltage avcc v ss - 0.5 v ss + 4.0 v input voltage vi v ss - 0.5 v cc + 0.5 v input voltage (nch-od) vind v ss - 0.5 v cc + 0.5 v analog pin input voltage via v ss - 0.5 av cc + 0.5 v output voltage vo v ss - 0.5 v cc + 0.5 v storage temperature tstg - 55 + 125 c
mb91230 series 44 2. recommended operating conditions mb91f233 mb91v230 mb91f233l, mb91f233m parameter symbol value unit remarks min max operating temperature ta - 40 + 85 c power supply voltage vcc 4.00 5.25 v *1 vcc3 3.00 3.60 v *4 vcc3b 2.20 3.60 v *2 vcc3io 3.00 3.60 v analog power supply voltage avcc 3.00 3.60 v lcd reference voltage v3 ? 5.25 v *3 parameter symbol value unit remarks min max operating temperature ta - 40 + 85 c power supply voltage vcc 4.00 5.25 v *1 vcc3 3.00 3.60 v vcc3b 3.00 3.60 v *2 vcc3io 3.00 3.60 v analog power supply voltage avcc 3.00 3.60 v lcd reference voltage v3 ? 5.25 v *3 parameter symbol value unit remarks min max operating temperature ta - 40 + 85 c power supply voltage vcc 3.00 3.60 v *1 vcc3 3.00 3.60 v *4 vcc3b 2.20 3.60 v *2 vcc3io 3.00 3.60 v analog power supply voltage avcc 3.00 3.60 v lcd reference voltage v3 ? 3.60 v *3
mb91230 series 45 mb91233l for normal use, set v cc 3 = v cc 3b = av cc = v cc 3io. *1 : the standard power-supply voltage varies with the model of product. *2 : only for backup. for normal use, set v cc 3 = v cc 3b = av cc = v cc 3io. *3 : v3 must not exceed vcc. *4 : for the relationships between v cc 3 and operating frequencies, see section 4.3 operation assurance range. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max operating temperature ta - 40 + 85 c power supply voltage vcc 3.00 3.60 v *1 vcc3 3.00 3.60 v *4 vcc3b 2.20 3.60 v *2 vcc3io 3.00 3.60 v analog power supply voltage avcc 3.00 3.60 v lcd reference voltage v3 ? 3.60 v *3
mb91230 series 46 3. dc characteristics mb91v230, mb91f233 parameter symbol pin name conditions value unit remarks min typ max power supply current icc v cc 3 flash model normal operation, ta = + 25 c, fcp = 33 mhz, fcpp = 16.5 mhz ? 84 95 ma icct rtc mode, @ta = + 25 c, fclk = 32 khz ? 20 50 m a watch timer, rtc, lcdc vcc3 = vcc3b = 2.4 v icch stop mode, @ta = + 25 c, fclk = 0 ? 550 m a iccs sleep mode ? 30 45 ma "h" level input voltage vih ?? v cc 0.8 ? v cc v x0a vcc3b = 2.2 v to 3.6 v v cc 3b 0.8 ? v cc 3b v when external clock is used l level input voltage vil ?? v ss ? v cc 0.2 v x0a vcc3b = 2.2 v to 3.6 v v ss ? v ss + 0.4 when external clock is used "h" level output voltage voh ? ioh = - 4 ma v cc - 0.5 ? v cc v "l" level output voltage vol ? iol = 4 ma v ss ? 0.4 v p64-67 iol = 20 ma input leakage current iil ??- 5 ? 5 m a open-drain output leakage current ileak ??- 10 ? 10 m a lcd division resistance rlcd v0-v1 v1-v2 v2-v3 ? 50 100 200 k w com0 to com3 output impedance rvcom com0 to com3 v1 to v3 = 5.0 v ?? 2.5 k w seg00 to seg31 output impedance rvseg seg00 to seg31 ?? 15 k w lcdc leakage current ilcdc v0 to v3, com0 to com3, seg00 to seg31 ?- 5 ? 5 m a
mb91230 series 47 mb91f233l, mb91233l parameter symbol pin name conditions value unit remarks min typ max power supply current icc vcc3 flash model normal operation, ta = + 25 c, fcp = 33 mhz, fcpp = 16.5 mhz ? 84 95 ma icc rom model normal operation, ta = + 25 c, fcp = 33 mhz, fcpp = 16.5 mhz ? 56 75 ma icct rtc mode, @ta = + 25 c, fclk = 32 khz ? 20 50 m a watch timer, rtc, lcdc vcc3 = vcc3b = 2.4 v icch stop mode, @ta = + 25 c, fclk = 0 ? 550 m a iccs sleep mode ? 30 45 ma "h" level input voltage vih ?? v cc 0.8 ? v cc v x0a vcc3b = 2.2 v to 3.6 v v cc 3b 0.8 ? v cc 3b v when external clock is used "l" level input voltag vil ?? v ss ? v cc 0.15 v x0a vcc3b = 2.2 v to 3.6 v v ss ? v ss + 0.4 ? when external clock is used "h" level output voltage voh ? vcc = 3.3 v, ioh = - 2 ma v cc - 0.5 ? v cc v "l" level output voltage vol ? iol = 2 ma v ss ? 0.4 v p64-67 iol = 10 ma input leakage current iil ??- 5 ? 5 m a open-drain output leakage current ileak ??- 10 ? 10 m a lcd division resistance rlcd v0-v1 v1-v2 v2-v3 ? 50 100 200 k w com0 to com3 output impedance rvcom com0 to com3 v1 to v3 = 5.0 v ?? 2.5 k w seg00 to seg31 output impedance rvseg seg00 to seg31 ?? 15 k w lcdc leakage current ilcdc v0 to v3, com0 to com3, seg00 to seg31 ?- 5 ?- 5 m a
mb91230 series 48 4. ac characteristics (1) main clock input standard (2) subclock input standard parameter sym- bol pin name condi- tions value unit remarks min typ max input frequency f c x0 ? 3.644.2mhz input clock cycle t cyl ?? 250 ? ns input clock pulse width ? p wh /t cyl p wl /t cyl 40 ? 60 % input clock rise time and fall time t cf t cr ??? 5ns at external clock internal operating clock frequency f cp ?? ?? 33.6 mhz parameter sym- bol pin name condi- tions value unit remarks min typ max input frequency f cl x0a ? ? 32.768 ? khz 28.571 32.768 35.714 at external clock input clock cycle t lcyl ? 28.0 ? 35.0 m s input clock pulse width ? p wlh /t lcyl p wll /t lcyl 45 ? 55 % input clock rise time and fall time ? t cf /t lcyl t cr /t lcyl ?? 5 % at external clock x0 0.8 v cc 3 0.8 v cc 3 v ss + 0.4 v ss + 0.4 0.8 v cc 3 t cyl p wh p wl t cf t cr x0a 0.8 v cc 3b 0.8 v cc 3b v ss + 0.4 v ss + 0.4 0.8 v cc 3b t lcyl p wlh p wll t cf t cr
mb91230 series 49 (3) operation assurance range 5. notes on the power-on sequence for dual-powered model based on 0.35 m m m m s technorogy ? power-on/off sequences power-on : v cc 3b, v cc 3 ? v cc ? v cc 3io, av cc , avrh, v0-v3 power-off : v cc 3io, av cc , avrh, v0-v3 ? v cc ? v cc 3, v cc 3b when v cc is turned on earlier, a potential difference between v cc and v cc 3 must fall within 3.6 v. the lcdc power supply v3 must not exceed v cc in voltage. apply v3 after turning on v cc 3. turn on v cc 3 before applying the analog power supply av cc or an analog signal. 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 32 khz5 10152025303540 mb91f233 mb91f233l mb91f233m mb91232l mb91233l pll off 8 mhz pll on 32 mhz@ 3.0 v 28 mhz@ 2.7 v 33.6 mhz@ 3.0 v 33.6 mhz@ 3.3 v 33.6 mhz@ 3.6 v internal voltage power supply v cc 3 [v] internal operation frequency [mhz]
mb91230 series 50 6. electrical characteristics for the a/d converter (v cc = av cc = 3.0 to 3.6 v, v ss = davs = av ss = 0 v, avrh = 3.0 v to 3.6 v, ta = 0 c to + 70 c) *1 : measured in the cpu sleep state *2 : it depends on the clock cycle supplied to peripheral resources. *3 : the current when the cpu is in stop mode and the a/d converter is not operaring. parameter value unit remarks min typ max resolution ?? 10 bit av cc = 3.3 v, at avrh = 3.3 v at cpu sleep mode total error* 1 - 5.0 ?+ 5.0 lsb nonlinear error* 1 - 3.5 ?+ 3.5 lsb differential linear error* 1 - 2.5 ?+ 2.5 lsb zero transition voltage* 1 - 2.0 + 1.0 + 6.0 lsb full transition voltage* 1 avrh - 5.5 avrh - 1.0 avrh + 3.0 lsb conversion time 1.69* 2 ??m s power supply voltage (analog + digital) ? 3.6 ? ma ?? 5 m a reference power supply current (between avrh and avrl) ? 470 ?m a avrh = 3.0 v, at avrl = 0.0 v ?? 10 m a at power-down* 3 analog input capacitance ? 40 ? pf inter-channel disparity ?? 4lsb r on1 r on2 c an0 to an7 analog input pin r on1 = approx. 100 w r on2 = approx. 60 w c1 = approx. 40 pf comparator
mb91230 series 51 7. electrical characteristics for the d/a converter (v cc = dav c = 3.0 v to 3.6 v, v ss = davs = 0 v, ta = 0 c to 70 c) the current consumption by this d/a converter varies with input digital code. this standard value indicates the current consumed when the digital code that maximizes the current consumption is input. parameter value unit remarks min typ max resolution ?? 8bit nonlinear error - 2.0 ?+ 2.0 lsb when the output is unloaded differential linear error - 1.0 ?+ 1.0 lsb when the output is unloaded conversion speed ? 0.6 ?m s when load capacitance (cl) = 20 pf ? 3.0 ?m s when load capacitance (cl) = 100 pf output impedance 2.0 2.9 3.8 k w analog current ? 40 ?m a 10 m s conversion, when the output is unloaded ?? 460 m a when the input digital code is fixed at 7ah or 85h ? 0.1 ?m a at power-down
mb91230 series 52 n n n n ordering information part number package remarks mb91v230cr-es 401-pin ceramic pga (pga-401c-a02) MB91F233PFF-GE1 120-pin plastic lqfp (fpt-120p-m05) mb91f233lpff-ge1 120-pin plastic lqfp (fpt-120p-m05) mb91f233llga-ge1 128-pin plastic flga (lga-128p-m01) mb91233lpff-g-xxx 120-pin plastic lqfp (fpt-120p-m05) mb91233llga-gxxx 128-pin plastic flga (lga-128p-m01)
mb91230 series 53 n n n n package dimensions (continued) 401-pin ceramic pga (pga-401c-a02) dimensions in mm (inches) . note : the values in parentheses are reference values. 48.26 ?0.55 (1.900 ?.022) sq index area 1994 fujitsu limited r401002sc-2-2 2.54 (.100) typ 0.40 ?0.10 (.016 ?.004) dia 45.72 (1.800) ref 1.20 ?0.25 (.047 ?.010) 5.27 (.207) max 3.40 ?0.40 (.134 ?.016) 1.00 (.039) dia typ (4 plcs) extra index pin 1.02 (.040) c typ (4 plcs) c
mb91230 series 54 (continued) 120-pin plastic lqfp (fpt-120p-m05) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. c 2003 fujitsu limited f120006s-c-4-5 0.07(.003) m index 16.000.20(.630.008)sq 14.000.10(.551.004)sq 130 31 60 91 120 61 90 lead no. (stand off) 0.100.10 (.004.004) 0.25(.010) (.024.006) 0.600.15 (.020.008) 0.500.20 (mounting height) 0~8 ? details of "a" part 1.50 +0.20 C0.10 +.008 C.004 .059 "a" 0.40(.016) 0.160.03 (.006.001) 0.1450.055 (.006.002) 0.08(.003) *
mb91230 series 55 (continued) 128-pin plastic flga (lga-128p-m01) dimensions in mm (inches) . note : the values in parentheses are reference values.
mb91230 series fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0401 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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